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71M6534 Datasheet(PDF) 92 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 92 Page - Maxim Integrated Products |
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92 / 132 page  71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 92 Rev 2 QREG[1:0] 201E[1:0] 0 NV R/W RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details. RST_SUBSEC 2010[0] 0 NV R/W The sub-second counter is restarted when a 1 is written to this bit. RTCA_ADJ[6:0] 2011[6:0] 40 – R/W Analog RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details. RTC_SEC[5:0 RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] 2015 2016 2017 2018 2019 201A 201B * * * * * * * NV NV NV NV NV NV NV R/W These are the year, month, day, hour, minute and second parameters of the RTC. Writing to these registers sets the time. Each write to one of these registers must be preceded by a write to 0x201F (WE). Valid values for each parameter are: SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight) DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12 YR: 00 to 99 (00 and all others divisible by 4 are leap years) Values in the RTC registers are undefined when the IC powers up without a battery but are maintained through mission and battery modes when a sufficient voltage is maintained at the VBAT pin. Write operations to these registers are delayed by one second. There is no change of value at reset if the voltage at VBAT is within specification. RTM_E 2002[3] 0 0 R/W Real Time Monitor enable (RTM). When 0, the RTM output is low. RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] 2060[9:8] 2061[7:0] 2062[9:8] 2063[7:0] 2064[9:8] 2064[7:0] 2065[9:8] 2066[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W The four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0. SECURE SFRB2[6] 0 – R/W When set, enables security provisions that prevent external reading of flash memory and CE program RAM (zeros will be returned if the memory is read). It should be set while PREBOOT is set. SECURE is cleared when the flash is mass-erased and on chip reset. The bit may only be set, attempts to write zero are ignored. SLEEP 20A9[6] 0 0 W Puts the 71M6533/71M6534 into SLEEP mode. This bit is ignored if system power is present. The 71M6533 and 71M6534 will wake when the autowake timer times out, when the push button is pushed, when system power returns or when RESET goes high. SEL_IAN SEL_IBN SEL_ICN SEL_IDN 20AC[1] 20AC[5] 20AD[1] 20AD[5] 0 0 0 0 0 0 0 0 R/W When set to 1, selects differential mode for the corresponding current input (IA, IB, IC, or ID). When 0, the input remains single-ended. SLOT0_SEL[3:0] SLOT1_SEL[3:0] … SLOT8_SEL[3:0] SLOT9_SEL[3:0] 2090[3:0] 2090[7:4] 2094[3:0] 2094[7:4] 0 1 … 8 9 0 1 … 8 9 R/W Primary multiplexer frame analog input selection. These bits map the selected input, 0-9 to the multiplexer state. The ADC output is always written to the memory location corresponding to the input, regardless of which multiplexer state an input is mapped to (see Section 1.1 Error! Not a valid result for table.). |
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