 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
71M6534 Datasheet(PDF) 91 Page - Maxim Integrated Products |
|
||||||||||||||||||||||||||||||
71M6534 Datasheet(HTML) 91 Page - Maxim Integrated Products |
|
|
91 / 132 page 
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Rev 2 91 OPT_RXDIS 2008[5] 0 0 R/W Configures OPT_RX to an analog input to the optical UART comparator or as a digital input/output, DIO1. 0 = OPT_RX, 1 = DIO1. OPT_RXINV 2008[4] 0 0 R/W Inverts the result from the OPT_RX comparator when 1. Affects only the UART input. Has no effect when OPT_RX is used as a DIO input. OPT_TXE[1:0] 2007[7:6] 00 00 R/W Configures the OPT_TX output pin. OPT_TXE[1:0] Function 00 OPT_TX 01 DIO2 10 WPULSE 11 RPULSE OPT_TXINV 2008[0] 0 0 R/W Inverts OPT_TX when 1. This inversion occurs before modulation. OPT_TXMOD 2008[1] 0 0 R/W Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated when it would otherwise have been zero. The modulation is applied after any inversion caused by OPT_TXINV. PLL_OK 2003[6] 0 0 R Indicates that system power is present and the clock generation PLL is settled. PLS_MAXWIDTH [7:0] 2080[7:0] FF FF R/W Determines the maximum width of the pulse (low going pulse). The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL. If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control is disabled and pulses are output with a 50% duty cycle. PLS_INTERVAL [7:0] 2081[7:0] 0 0 R/W For PULSE_W and PULSE_V only, if the FIFO is used, PLS_INTERVAL must be set to 81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the CE issues them. PLS_INV 2004[6] 0 0 R/W Inverts the polarity of the pulse outputs Normally, these pulses are active low. When inverted, they become active high. PREBOOT SFRB2[7] – – R Indicates that the preboot sequence is active. PREG[16:0] 201C[2:0] 201D[7:0] 201E[7:2] 4 0 0 NV NV NV R/W R/W R/W RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details. 0x0FFBF ≤ PREG ≤ 0x10040 PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a single number calculated by the MPU. . PREG[16:0] and QREG[1:0] are non-volatile, but have no correcting function in SLEEP mode. PRE_SAMPS[1:0] 2001[7:6] 0 0 R/W The duration of the pre-summer, in samples. PRE_SAMPS[1:0] Pre-Summer Duration 00 42 01 50 10 84 11 100 |
|
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
