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71M6534 Datasheet(PDF) 90 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
Download  132 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 90 Page - Maxim Integrated Products

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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
90
Rev 2
LCD_Y
2021[6]
0
L
R/W
LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
0 =
1 Hz (500 ms ON, 500 ms OFF)
1 =
0.5 Hz (1 s ON, 1 s OFF)
M26MHZ
M40MHZ
2005[4]
2005[0]
0
0
0
0
R/W
R/W
M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ are
ignored.
M40MHZ M26MHZ
MCK Frequency
0
0
20 MHz
0
1
26.7 MHz
1
0
40 MHz
1
1
40 MHz
MPU_DIV[2:0]
2004[2:0]
0
0
R/W
The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
MPU_DIV[2:0]
Resulting Clock Frequency
000
MCK/4
001
MCK/8
010
MCK/16
011
MCK/32
100
MCK/64
101
MCK/128
110
MCK/265
111
MCK/265
MUX_ALT
2005[2]
0
0
R/W
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E is 00, MUX_ALT is automatically asserted once per sum cycle, when
XFER_BUSY falls.
MUX_DIV[3:0]
209D[3:0]
0
0
R/W The number of states in the input multiplexer.
MUX_SYNC_E
2020[7]
0
0
R/W When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
OPT_FDC[1:0]
2007[1:0]
0
0
R/W
Selects the modulation duty cycle for OPT_TX.
OPT_FDC[1:0]
Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low


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