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71M6534 Datasheet(PDF) 83 Page - Maxim Integrated Products |
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71M6534 Datasheet(HTML) 83 Page - Maxim Integrated Products |
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83 / 132 page  FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Rev 2 83 5.2 I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: • Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx. • Bits with an R (read) direction can be read by the MPU. • Columns labeled Reset and Wake describe the bit values upon reset and wake, respectively. “NV” in the Wake column means the bit is powered by the nonvolatile supply and is not initialized. LCD-related registers labeled “L” retain data upon transition from LCD mode to BROWNOUT mode and vice versa, but do not retain data in SLEEP mode. “–“ means that the value is undefined. • Write-only bits will return zero when they are read. • Bits marked with an asterisk (e.g. DIO_DIR1[4]†) are applicable to the 71M6534 only. Table 54: I/O RAM Description – Alphabetical (by Bit Name) Name Location Reset Wake Dir Description ADC_E 2005[3] 0 0 R/W Enables ADC and VREF. When disabled, removes bias current. BME 2020[6] 0 – R/W Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles. See the MUX_ALT bit. BOOT_SIZE[7:0] 20A7[7:0] 01 01 R/W End of space reserved for boot program. The ending address of the boot region is 1024*BOOT_SIZE. CE10MHZ 2000[3] 0 0 R/W CE clock select. When set, the CE is clocked at 10 MHz. Otherwise, the CE clock frequency is 5 MHz. CE_E 2000[4] 0 0 R/W CE enable. CE_LCTN[7:0] 20A8[7:0] 0x31 0x31 R/W CE program location. The starting address for the CE program is 1024*CE_LCTN. CHOP_E[1:0] 2002[5:4] 00 00 R/W Chop enable for the reference bandgap circuit. The value of CHOP will change on the rising edge of MUXSYNC according to the value in CHOP_E: 00 = toggle, except at the mux sync edge at the end of SUMCYCLE, an alternative MUX frame is automatically inserted at the end of each accumulation interval. 01 = positive. 10 = reversed. 11 = toggle, no alternative MUX frame is inserted CHOP_I_EN 20AB[0] 0 0 R/W When CHOP_I_EN is set, chop mode for the analog current inputs can be enabled with the CHOP_IA, CHOP_IB, CHOP_IC, and CHOP_ID bits. CHOP_IA CHOP_IB CHOP_IC CHOP_ID 20AC[0] 20AC[4] 20AD[0] 20AD[4] 0 0 0 0 0 0 0 0 R/W When CHOP_I_EN is set, these bits enable chop mode for the respective channel. |
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