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71M6534 Datasheet(PDF) 65 Page - Maxim Integrated Products

Part No. 71M6534
Description  Exceeds IEC 62053/ANSI C12.20 Standards
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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71M6534 Datasheet(HTML) 65 Page - Maxim Integrated Products

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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Rev 2
65
2.4 Fault and Reset Behavior
2.4.1 Reset Mode
When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to
run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the
power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This
will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin
executing its pre-boot and boot sequences from address 00. See the description of Program Security
in Section 1.5.5 for additional descriptions of pre-boot and boot.
If system power is not present, the reset timer duration will be 2 cycles of the crystal clock at which time
the MPU will begin executing in BROWNOUT mode, starting at address 00.
2.4.2 Power Fault Circuit
The 71M6533 and 71M6534 include a comparator to monitor system power fault conditions. When the
output of the comparator falls (V1<VBIAS), the I/O RAM PLL_OK bit is zeroed and the part switches to
BROWNOUT mode, if a battery is present (and the MPU keeps executing code). If a battery is not
present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode. Once system
power returns the MPU remains in reset and does not transition to MISSION mode until 2048 to 4096
CK32 clock cycles later, when PLL_OK rises. .
There are several conditions the device could be in as system power returns. If the part is in BROWNOUT
mode, it will automatically switch to MISSION mode when PLL_OK rises. It will receive an interrupt indicating
this. No configuration bits will be reset or reconfigured during this transition.
If the part is in LCD or SLEEP mode when system power returns, it will also switch to MISSION mode
when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having
been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware
watchdog timer will become active when the part enters MISSION mode.
If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK
rises. All configuration bits will be in reset state, and RTC and MPU RAM data will be unknown and must
be initialized by the MPU.
2.5 Wake Up Behavior
As described above, the part will always wake up in MISSION mode when system power is restored.
Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or when
a timeout of the wake-up timer occurs.
2.5.1 Wake on PB
If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally
pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU
is in reset due to WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU
begins to execute. The MPU can determine whether the PB signal woke it up by checking the IE_PB flag.
Figure 28 shows the Wake Up timing.
For debouncing, the PB pin is monitored by a state machine operating from a 32 Hz clock. This circuit will
reject between 31 ms and 62 ms of noise. Detection hardware will ignore all transitions after the initial
rising edge. This will continue until the MPU clears the IE_PB bit.


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