R1LV0816ASD –5SI, 7SI

Preliminary

REJ03C0397-0001 Rev.0.01

2009.12.08

Page 9 of 16

Write Cycle

R1LV0816ASD-5SI

(Note 0)

R1LV0816ASD-7SI

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Note

Write cycle time

55

-

70

-

ns

Address valid to end of write

50

-

65

-

ns

Chip select to end of write

50

-

65

-

ns

5

Write pulse width

40

-

55

-

ns

4

LB#, UB# valid to end of write

50

-

65

-

ns

Address setup time

0

-

0

-

ns

6

Write recovery time

0

-

0

-

ns

7

Data to write time overlap

25

-

35

-

ns

Data hold from write time

0

-

0

-

ns

Output enable from end of write

5

-

5

-

ns

2

Output disable to output in high-Z

0

20

0

25

ns

1,2

Write to output in high-Z

0

20

0

25

ns

1,2

Note 0. If Vcc is 2.4-2.7V, parameters of R1LV0816ASA-7SI and R1LV0816ASD-7SI7SI are applied.

and are not referred to output voltage levels.

2. Typical parameter is sampled and not 100% tested.

from device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or low UB#.

A write begins at the latest transitions among CS1# going low, CS2 going high, WE# going low and LB#

going low or UB# going low.

A write ends at the earliest transitions among CS1# going high, CS2 going low, WE# going high and LB#