R1EX25008Axx00I/R1EX25016Axx00I

Data Protect

The protection features of the device are summarized in the following table. When the Status Register Write Disable

(SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

weather write protect (W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered,

depending on the state of write protect (W):

 If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.

 If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch

(WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status

Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory

area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also

hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

 By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low.

 By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high.

If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the

Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Write Protected Block Size

Status register bits

Array addresses protected

BP1

BP0

Protected blocks

R1EX25016A

R1EX25008A

0

0

None

None

None

0

1

Upper quarter

600h − 7FFh

300h − 3FFh

1

0

Upper half

400h − 7FFh

200h − 3FFh

1

1

Whole memory

000h − 7FFh

000h − 3FFh

Protection Modes

Memory protect

signal

SRWD bit

Mode

Write protection of the

status register

Protected area*

1

Unprotected area*

1

1

0

Software

protected (SPM)

Status register is writable

(if the WREN) instruction

has set the WEL bit).

The values in the BP1

and BP0 bits can be

changed.

Write protected

Ready to accept Write

instructions

0

0

1

1

0

1

Hardware

protected (HPM)

Status register is

hardware write

protected. The values in

the BP1 and BP0 bits

cannot be changed.

Write protected

Ready to accept Write

instructions

Note:

1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the

former table.

REJ03C0396-0100 Rev.1.00 Nov.24.2009

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