Semiconductor Group

10

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

Notes:

1) All voltages are referenced to

2)

3)

4) Address can be changed once or less while RAS =

a hyper page mode (EDO) cycle

5) An initial pause of 200

µs is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,

a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume

7)

measured between

8) Measured with the specified current load and 100 pF at

by the latter of

9) Operation within the

only. If

10) Operation within the

only. If

11) Either

12)

referenced to output voltage levels.

last.

13) Either

14) Either

electrical characteristics only. If

open-circuit (high impedance) through the entire cycle; if

the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above

sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.