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KSZ8842-16MBL-EVAl Datasheet(PDF) 68 Page - Micrel Semiconductor |
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KSZ8842-16MBL-EVAl Datasheet(HTML) 68 Page - Micrel Semiconductor |
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68 / 141 page  Micrel, Inc. KSZ8842-16/32 MQL/MVL/MVLI/MBL October 2007 68 M9999-102207-1.9 Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment is set, it will automatically increment the RXQ Pointer on read accesses to the data register. The counter is incremented is by one for every byte access, by two for every word access, and by four for every double word access. Bit Default Value R/W Description 15 - RO Reserved 14 0x0 RW RXFPAI RX Frame Pointer Auto Increment When this bit is set, the RXQ Address register increments automatically on accesses to the data register. The increment is by one for every byte access, by two for every word access, and by four for every double word access. When this bit is reset, the RX frame data pointer is manually controlled by user to access the RX frame location. 13-11 - RO Reserved 10-0 0x0 RW RXFP RX Frame Pointer RX Frame data pointer index to the Data register for access. This field reset to next available RX frame location when RX Frame release command is issued (through the RXQ command register). Bank 17 QMU Data Register Low (0x08): QDRL This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps from the RXQ, and writing maps to the TXQ. Bit Default Value R/W Description 15-0 - RW QDRL Queue Data Register Low This register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the KSZ8842M regardless of whether the pointer is even, odd, or Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This register along with DQRH is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations. Bank 17 QMU Data Register High (0x0A): QDRH This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading maps from the RXQ, and writing maps to the TXQ. Bit Default Value R/W Description 15-0 - RW QDRL Queue Data Register High This register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the KSZ8842M regardless of whether the pointer is even, odd, or dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This register along with DQRL is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations. |
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