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KSZ8842-16MBL-EVAl Datasheet(PDF) 64 Page - Micrel Semiconductor |
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KSZ8842-16MBL-EVAl Datasheet(HTML) 64 Page - Micrel Semiconductor |
64 / 141 page Micrel, Inc. KSZ8842-16/32 MQL/MVL/MVLI/MBL October 2007 64 M9999-102207-1.9 Bank 3 Memory BIST INFO Register (0x04): MBIR Bit Default Value R/W Description 15-13 0x0 RO Reserved 12 - RO TXMBF TX Memory Bist Finish When set, it indicates the Memory Built In Self Test completion for the TX Memory. 11 - RO TXMBFA TX Memory Bist Fail When set, it indicates the Memory Built In Self Test has failed. 10-5 - RO Reserved 4 - RO RXMBF RX Memory Bist Finish When set, it indicates the Memory Built In Self Test completion for the RX Memory. 3 - RO RXMBFA RX Memory Bist Fail When set, it indicates the Memory Built In Self Test has failed. 2-0 - RO Reserved Bank 3 Global Reset Register (0x06): GRR This register controls the global reset function with information programmed by the CPU. Bit Default Value R/W Description 15-1 0x0000 RO Reserved 0 0 RW Global Soft Reset 1: software reset is active. 0: software reset is inactive. Software reset will affect PHY, MAC, QMU, DMA, and the switch core, only the BIU (base address registers) remains unaffected by a software reset. Bank 3 Bus Configuration Register (0x08): BCFG This register is a read-only register. The bit 0 is automatically downloaded from bit 0 Configparm word of EEPROM, if pin EEEN is high (enabled EEPROM) Bit Default Value R/W Description 15-1 0x0000 RO Reserved 0 - RO Bus Configuration (only for KSZ8842-16 device) 1: bus width is 16 bits. 0: bus width is 8 bits. (this bit is only avaiable when EEPROM is enabled) Banks 4 – 15: Reserved Except Bank Select Register (0xE). |
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