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KS8995M Datasheet(PDF) 59 Page - Micrel Semiconductor |
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KS8995M Datasheet(HTML) 59 Page - Micrel Semiconductor |
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59 / 76 page  July 2006 59 M9999-070506 KS8995M Micrel, Inc. (2) MIB counter read (read port 2 rx 64 counter) Write to reg110 with 0x1c (read MIB counter selected) Write to reg111 with 0x2e (trigger the read operation ) Then Read reg117 (counter value 31-24) // If bit 31 = 1, there was a counter overflow. // If bit 30 = 0, restart (reread) from this register. Read reg118 (counter value 23-16) Read reg119 (counter value 15-8) Read reg120 (counter value 7-0) (3) MIB counter read (read port 1 tx drop packets) Write to reg 110 with 0x1d Write to reg 111 with 0x00 Then Read reg119 (counter value 15-8) Read reg120 (counter value 7-0) Note: To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 200 = 260ms, where there are 160 register, 3 overhead, 8 clocks per access, at 5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters. |
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