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KSZ8841-16MVLI Datasheet(PDF) 53 Page - Micrel Semiconductor |
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KSZ8841-16MVLI Datasheet(HTML) 53 Page - Micrel Semiconductor |
53 / 105 page Micrel, Inc. KSZ8841-16/32 MQL/MVL/MBL October 2007 53 M9999-102207-1.6 Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR This register contains the user defined QMU RX Queue high watermark configuration bit as below. Bit Default Value R/W Description 15-13 0x0 RO Reserved 12 0 RW QMU RX Flow Control High Watermark Configuration 0: 3 KBytes 1: 2 KBytes 11-0 0x000 RO Reserved Bank 0 Bus Error Status Register (0x06): BESR This register flags the different kinds of errors on the host bus. Bit Default Value R/W Description 15 0 RO IBEC Illegal Byte Enable Combination 1: illegal byte enable combination occurs. The illegal combination value can be found from bit 14 to bit 11. 0: legal byte enable combination. Write 1 to clear. 14-11 - RO IBECV Illegal Byte Enable Combination Value Bit 14: byte enable 3. Bit 13: byte enable 2. Bit 12: byte enable 1. Bit 11: byte enable 0. This value is valid only when bit 15 is set to 1. 10 0 RO SSAXFER Simultaneous Synchronous and Asnychronous Transfers 1: Synchronous and Asnychronous Transfers occur simultaneously. 0: normal. Write 1 to clear. 9-0 0x000 RO Reserved. Bank 0 Bus Burst Length Register (0x08): BBLR Before the burst can be sent, the burst length needs to be programmed. Bit Default Value R/W Description 15 0 RO Reserved. 14-12 0x0 RW BRL Burst Length (for burst read and write) 000: single. 011: fixed burst read length of 4. 101: fixed burst read length of 8. 111: fixed burst read length of 16. 11-0 0x000 RO Reserved. Bank 1: Reserved Except Bank Select Register (0xE). |
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