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KSZ8873FLLI Datasheet(PDF) 10 Page - Micrel Semiconductor |
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KSZ8873FLLI Datasheet(HTML) 10 Page - Micrel Semiconductor |
10 / 108 page Micrel, Inc. KSZ8873MLL/FLL/RLL September 2011 10 M9999-092111-1.5 List of Tables Table 1. FX Signal Threshold............................................................................................................................................... 18 Table 2. MDI/MDI-X Pin Definitions ..................................................................................................................................... 18 Table 3. Internal Function Block Status ................................................................................................................................ 23 Table 4. MII Signals ............................................................................................................................................................. 28 Table 5. RMII Clock Setting .................................................................................................................................................. 29 Table 6. RMII Signal Description.......................................................................................................................................... 30 Table 7. RMII Signal Connections........................................................................................................................................ 30 Table 8. MII Management Interface Frame Format ............................................................................................................. 31 Table 9. Serial Management Interface (SMI) Frame Format ............................................................................................... 31 Table 10. FID+DA Lookup in VLAN Mode ........................................................................................................................... 32 Table 11. FID+SA Lookup in VLAN Mode ........................................................................................................................... 32 Table 12. Spanning Tree States .......................................................................................................................................... 35 Table 13. SPI Connections .................................................................................................................................................. 40 Table 14. Data Rate Limit Table .......................................................................................................................................... 62 Table 15. Format of Static MAC Table (8 Entries)............................................................................................................... 85 Table 16. Format of Static VLAN Table (16 Entries)............................................................................................................ 87 Table 17. Format of Dynamic MAC Address Table (1K Entries) ......................................................................................... 88 Table 18. Format of “Per Port” MIB Counters ...................................................................................................................... 89 Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets.................................................................................. 90 Table 20. Format of “All Port Dropped Packet” MIB Counters............................................................................................. 90 Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets...................................................................... 91 Table 22. EEPROM Timing Parameters .............................................................................................................................. 94 Table 23. MAC Mode MII Timing Parameters...................................................................................................................... 95 Table 24. PHY Mode MII Timing Parameters ...................................................................................................................... 96 Table 25. RMII Timing Parameters ...................................................................................................................................... 97 Table 26. I2C Timing Parameters ........................................................................................................................................ 99 Table 27. SPI Input Timing Parameters............................................................................................................................. 100 Table 28. SPI Output Timing Parameters .......................................................................................................................... 101 Table 29. Auto-Negotiation Timing Parameters................................................................................................................. 102 Table 30. MDC/MDIO Timing Parameters ......................................................................................................................... 103 Table 31. Reset Timing Parameters .................................................................................................................................. 104 Table 32. Transformer Selection Criteria ........................................................................................................................... 106 Table 33. Qualified Single Port Magnetics......................................................................................................................... 106 Table 34. Typical Reference Crystal Characteristics......................................................................................................... 106 |
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