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KSZ8873MLL Datasheet(PDF) 12 Page - Micrel Semiconductor |
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KSZ8873MLL Datasheet(HTML) 12 Page - Micrel Semiconductor |
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12 / 108 page  Micrel, Inc. KSZ8873MLL/FLL/RLL September 2011 12 M9999-092111-1.5 Pin Description and I/O Assignment (Continued) Pin Number Pin Name Type (1) Description 28 SMRXDV3 lpu/O Switch MII receive data valid Strap option: MII mode selection PU = PHY mode. PD = MAC mode (In MAC mode, port 3 MII has to connect a powered active external PHY for the normal operation) 29 SMRXD33/ REFCLKO_3 lpu/O MLL/FLL: Switch MII receive data bit 3/ RLL: Output reference clock in RMII mode. Strap option: enable auto-negotiation on port 2 (P2ANEN) PU = enable P2ANEN PD = disable P2ANEN 30 SMRXD32 Ipu/O Switch MII/RMII receive data bit 2 Strap option: Force the speed on port 2 PU = force port 2 to 100BT if P2ANEN = 0 PD = force port 2 to 10BT if P2ANEN = 0 31 SMRXD31 Ipu/O Switch MII/RMII receive data bit 1 Strap option: Force duplex mode (P2DPX) PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0. PD = Port 2 set to half duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0. 32 GND Gnd Digital ground 33 SMRXD30 lpu/O Switch MII receive data bit 0 Strap option: Force flow control on port 2 (P2FFC) PU = always enable (force) port 2 flow control feature, regardless of Auto- Negotiation result. PD = port 2 flow control is enabled by auto- negotiation result. 34 SCRS3/ NC Ipu/O MLL/FLL: Switch MII carrier sense RLL: No connection, Internal pull up. 35 SCOL3/ NC Ipu/O MLL/FLL: Switch MII collision detect RLL: No connection, Internal pull up. 36 SMRXC3/ NC I/O MLL/FLL: Switch MII receive clock. Output in PHY MII mode Input in MAC MII mode RLL: No Connection. 37 GND Gnd Digital ground 38 VDDC P 1.8V digital core power input from VDDCO (pin 56). 39 SPIQ lpu/O SPI slave mode: serial data output Note: an external pull-up is needed on this pin when it is in use. Strap option: XCLK Frequency Selection PU = 25 MHz PD = 50 MHz 40 SPISN Ipu SPI slave mode: chip select (active low) When SPISN is high, the KSZ8873MLL/FLL/RLL is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. Note: an external pull-up is needed on this pin when it is in use. |
Similar Part No. - KSZ8873MLL_11 |
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Similar Description - KSZ8873MLL_11 |
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