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MIC2310-1ZTS Datasheet(PDF) 18 Page - Micrel Semiconductor |
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MIC2310-1ZTS Datasheet(HTML) 18 Page - Micrel Semiconductor |
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18 / 34 page  Micrel, Inc. MIC2310 July 2008 18 M9999-070108-A VCC = 12V, nominal VGSPGH VGSPGH VPGH VPGL tPOC IPOC VREG = 5V, nominal tRETRY tPOR VCC & VREG ENABLE GATE VOUT ILOAD CRETRY PWRGD I_FLT DISCH VVREG(UVLOH) Figure 6. Primary Overcurrent Fault with Auto-Retry to Reset the Circuit Breaker HW_FLT Digital Output Asserted by a MOSFET DG Short with ENABLE = LOW In order to protect the system from the result of the installation of a damaged MOSFET on the PCB, the controller incorporates a MOSFET shorted DG detection scheme whose operation is described in Figure 7. With the applied VCC supply high such that the internal VREG voltage is above the controller’s VVREG(UVLOH) threshold voltage, an elapsed POR timer, and with the ENABLE input LOW, a weak current sink at the GATE pin attempts to hold the GATE voltage at 0V. If there is a DG short on the MOSFET, the weak current sink is not capable of holding the voltage at 0V as the GATE voltage tracks the MOSFET’s DRAIN voltage. The voltage monitor circuit at the controller’s GATE pin will be triggered once the GATE voltage crosses the VGATEFT(EXT) threshold voltage. The HW_FLT digital output is subsequently asserted within a delay approximately equal to the delay in the logic circuits – no additional timing circuit is required. To clear the latched GATE voltage monitor circuit and to reset the HW_FLT digital output, the applied VCC supply voltage must fall such that VREG is below the controller’s VVREG(UVLOL) threshold voltage. |
Similar Part No. - MIC2310-1ZTS |
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Similar Description - MIC2310-1ZTS |
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