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MICRF220 Datasheet(PDF) 9 Page - Micrel Semiconductor

Part # MICRF220
Description  300MHz to 450MHz, 3.3V ASK/OOK Receiver with RSSI and Squelch
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MICRF220 Datasheet(HTML) 9 Page - Micrel Semiconductor

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Micrel, Inc.
MICRF220
August 2010
9
M9999-082610-A
Detector and Programmable Low-Pass Filter
The demodulation starts with the detector removing the
carrier from the IF signal. Post detection, the signal
becomes baseband information. The low-pass filter further
enhances the baseband signal. There are four selectable
low-pass filter BW settings; 1625Hz, 3250Hz, 6500Hz, and
13000Hz for 433.92MHz operation. The low-pass filter BW
is directly proportional to the crystal reference frequency,
and hence RF Operating Frequency. Filter BW values can
be easily calculated by direct scaling. Equation 5 illustrates
filter Demod BW calculation:
BWOperating Freq = BW@433.92MHz ×
433.92
(MHz)
Freq
Operating
Eq. 5
It is very important to choose the baseband bandwidth
setting suitable for the data rate to minimize bit error rate.
Use the operating curves that show BER vs. bit rates for
different SEL1, SEL0 settings as a guide.
This low-pass filter -3dB corner, or the demodulation BW,
is set at 13000Hz @ 433.92MHz as default (assuming both
SEL0 and SEL1 pins are floating, internal pull-up resistors
set the voltage to VDD). The low-pass filter can be hardware
set by external pins SEL0 and SEL1. Table 2 demonstrates
the scaling for 315MHz RF frequency:
VSEL1
VSEL0
Low-Pass
Filter BW
Maximum Encoded
Bit Rate
GND
GND
1625Hz
2.5kbps
GND
VDD
3250Hz
5kbps
VDD
GND
6500Hz
10kbps
VDD
VDD
13000Hz
20kbps
Table 1. Low-Pass Filter Selection @ 434MHz RF Input
VSEL1
VSEL0
Low-Pass
Filter BW
Maximum Encoded
Bit Rate
GND
GND
1170Hz
1.8kbps
GND
VDD
2350Hz
3.6kbps
VDD
GND
4700Hz
7.2kbps
VDD
VDD
9400Hz
14.4kbps
Table 2. Low-Pass Filter Selection @ 315MHz RF Input
Slicer and CTH
The signal prior to the slicer, labeled “Audio Signal” in
Figure 1, is still baseband analog signal. The data slicer
converts the analog signal into ones and zeros based upon
50% of the slicing threshold voltage built up in the CTH
capacitor. After the slicer, the signal is demodulated OOK
digital data. When there is only thermal noise at ANT pin,
the voltage level on CTH pin is about 650mV. This voltage
starts to drop when there is RF signal present. When the
RF signal level is greater than
−100dBm, the voltage is
about 400mV.
The value of the capacitor from CTH pin to GND is not
critical to the sensitivity of MICRF220, although it should be
large enough to provide a stable slicing level for the
comparator. The value used in the evaluation board of
0.1μF is good for all bit rates from 500bps to 20kbps.
CTH Hold Mode
If the internal demodulated signal (DO
′ in Figure 1) is at
logic LOW for more than about 4msec, the chip
automatically enters CTH hold mode, which holds the
voltage on CTH pin constant even without RF input signal.
This is useful in a transmission gap, or “deadtime”, used in
many encoding schemes. When the signal reappears, CTH
voltage does not need to re-settle, improving the time to
output with no pulse width distortion, or time to good data
(TTGD).
AGC Loop and CAGC
The AGC comparator monitors the signal amplitude from
the output of the programmable low-pass filter. The AGC
loop in the chip regulates the signal at this point to be at a
constant level when the input RF signal is within the AGC
loop dynamic range (about
−115dBm to −40dBm).
When the chip first turns on, the fast charge feature
charges the CAGC node up with 120µA typical current.
When the voltage on CAGC increases, the gains of the
mixer and IF amplifier go up, increasing the amplitude of
the audio signal (as labeled in Figure 1), even with only
thermal noise at the LNA input. The fast-charge current is
disabled when the audio signal crosses the slicing
threshold, causing DO’ to go high, for the first time.
When an RF signal is applied, a fast attack period ensues,
when 600µA current discharges the CAGC node to reduce
the gain to a proper level. Once the loop reaches
equilibrium, the fast attack current is disabled, leaving only
15µA to discharge CAGC or 1.5µA to charge CAGC. The
fast attack current is enabled only when the RF signal
increases faster than the ability of the AGC loop to track it.


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