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SY100ELT22ZITR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100ELT22ZITR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 5 page 1 SY10ELT22 SY100ELT22 Micrel, Inc. M9999-052108 hbwhelp@micrel.com or (408) 955-1690 Pin Function Qn Differential PECL Outputs Dn TTL Inputs VCC +5.0V Supply GND Ground DESCRIPTION s 300ps typical propagation delay s <100ps output-to-output skew s Differential PECL outputs s PNP TTL inputs for minimal loading s Flow-through pinouts s Available in 8-pin SOIC package The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the tranlation of a clock and a data signal. The ELT22 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels. FEATURES DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR PIN NAMES SY10ELT22 SY100ELT22 Rev.: H Amendment: /0 Issue Date: May 2008 |
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