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TRF3765 Datasheet(PDF) 6 Page - Texas Instruments |
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TRF3765 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 51 page TRF3765 SLWS230C – SEPTEMBER 2011 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA; BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register Definitions section, and standard operating condition, unless otherwise noted. Table of Graphs Open-Loop Phase Noise vs Temperature(1) Figure 1, Figure 2, Figure 3, Figure 4 Open-Loop Phase Noise vs Voltage(1) Figure 5, Figure 6, Figure 7, Figure 8 Open-Loop Phase Noise vs Temperature(1)(2) Figure 9, Figure 10, Figure 11, Figure 12 Open-Loop Phase Noise vs Voltage(1)(2) Figure 13, Figure 14, Figure 15, Figure 16 Figure 17, Figure 18, Figure 19, Figure 20, Closed-Loop Phase Noise vs Temperature(3) Figure 21, Figure 22, Figure 23 Figure 24, Figure 25, Figure 26, Figure 27, Closed-Loop Phase Noise vs Temperature(2)(3) Figure 28, Figure 29, Figure 30 Closed-Loop Phase Noise vs Divide Ratio(3) Figure 31 Closed-Loop Phase Noise vs Divide Ratio(2)(3) Figure 32 Figure 33, Figure 34, Figure 35, Figure 36, Closed-Loop Phase Noise vs Temperature(4) Figure 37, Figure 38, Figure 39 Figure 40, Figure 41, Figure 42, Figure 43, Closed-Loop Phase Noise vs Temperature(2)(4) Figure 44, Figure 45, Figure 46 Closed-Loop Phase Noise vs Divide Ratio(4) Figure 47 Closed-Loop Phase Noise vs Divide Ratio(2)(4) Figure 48 PFD Spurs vs Temperature(4) Figure 49 Multiples of PFD Spurs(4) Figure 50, Figure 51, Figure 52 Multiples of PFD Spurs(4)(5) Figure 53 Fractional Spurs vs LO Divider(3) Figure 54 Fractional Spurs vs RF Divider and Prescaler(3) Figure 55 Fractional Spurs vs Temperature(3) Figure 56 Multiples of PFD Spurs(3) Figure 57 LO Harmonics(4) Figure 58 Output Power with Multiple Buffers(4) Figure 59, Figure 60 Output Power vs Output Port(4) Figure 61 Output Power vs Buffer Bias(4) Figure 62 VCO Gain (Kv) vs Frequency Figure 63 (1) VCO_TRIM = 32, VTUNE_IN = 1.1 V, CP_TRISTATE = 3 (3-state), and CAL_BYPASS = On. (2) VCO_BIAS = 600 µA. (3) Reference frequency = 61.44 MHz; PFD frequency = 30.72 MHz. (4) Reference frequency = 40 MHz; PFD frequency = 1.6 MHz. (5) Performance change at frequencies above 1500 MHz results from PLL_DIV_SEL changing from divide-by-1 to divide-by-2. 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TRF3765 |
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