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SY100S350

Micrel, Inc.

M9999-042307

hbwhelp@micrel.com or (408) 955-1690

HEX D-LATCH

SY100S350

s Max. transparent propagation delay of 900ps

s Min. Master Reset and Enable pulse widths of 100ps

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Voltage and temperature compensation for improved

noise immunity

s Internal 75k

s More than 40% faster than Fairchild

s Approximately 30% lower power than Fairchild

s Function and pinout compatible with Fairchild F100K

s Available in 28-pin PLCC package

FEATURES

DESCRIPTION

The SY100S350 offers six high-speed D-Latches with

both true and complement outputs, and is performance

compatible for use with high-performance ECL systems.

either or both of the enable signals are at a logic HIGH, then

the latches store the last valid data present on its inputs

(MR) overrides all other input signals and takes the outputs

to a logic LOW state. All inputs have 75k

Ω pull-down

resistors.

Rev.: I

Amendment: /0

Issue Date:

April 2007

BLOCK DIAGRAM

D

R

E

D

R

E

D

R

E

D

R

E

D

R

E

D

R

E

MR

Pin

Function

Data Inputs

Common Enable Inputs (Active LOW)

MR

Asynchronous Master Reset Input

Data Outputs

Complementary Data Outputs

PIN NAMES