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SY100S360JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S360JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY100S360 Micrel, Inc. M9999-042307 hbwhelp@micrel.com or (408) 955-1690 BLOCK DIAGRAM I0a Za I1a C Zb I2a I3a I4a I5a I6a I7a Ia I0b I1b I2b I3b I4b I5b I6b I7b Ib SY100S360 DUAL PARITY CHECKER/ GENERATOR s Max. propagation delay of 2200ps s IEE min. of –70mA s Industry standard 100K ECL levels s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75k Ω input pull-down resistors s 15% faster than Fairchild 300K s Approximately 30% lower power than Fairchild 300K s Function and pinout compatible with Fairchild F100K s Available in 28-pin PLCC package FEATURES DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs (Ia, Ib) has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data. A Compare output (C) is also provided which allows comparison of two 8-bit words. A logic LOW on the C output indicates a match. The inputs on this device have 75k Ω pull-down resistors. Rev.: I Amendment: /0 Issue Date: April 2007 |
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