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SY58024UMG Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY58024UMG Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 11 page 5 Precision Edge® SY58024U Micrel, Inc. M9999-082807 hbwhelp@micrel.com or (408) 955-1690 VCC = +2.5V ±5% or +3.3V ±10%; RL = 100Ω across each output pair; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Operating Frequency V IN ≥ 100mV; VOUT ≥ 200mV Clock 6 GHz NRZ Data 10.7 Gbps tpd Propagation Delay IN-to-Q 200 350 ps SEL-to-Q 100 400 ps tSKEW Channel-to-Channel Skew (Within Bank) Note 8 20 ps Part-to-Part Skew Note 9 75 ps tJITTER Clock Cycle-to-Cycle Jitter Note 10 1psRMS Total Jitter Note 11 10 psPP Data Random Jitter Note 12 1psRMS Deterministic Jitter Note 13 10 psPP Crosstalk Induced Jitter Note 14 0.7 psRMS Adjacent Channel tr, tf Output Rise/Fall Time 20% to 80% at full swing. 25 60 ps Notes: 7. High frequency AC-parameters are guaranteed by design and characterization. 8. Skew is measured between outputs of the same bank under identical transitions. 9. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T n–Tn–1 where T is the time between rising edges of the output signal. 11. Total jitter definition: With an ideal clock input of frequency ≤ fMAX, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 12. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps–3.2Gbps. 13. Deterministic jitter is measured at 2.5Gbps–3.2Gbps with both K28.5 and 223–1 PRBS pattern. 14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying similar, differential clock frequencies that are asynchronous with respect to each other at inputs. AC ELECTRICAL CHARACTERISTICS(7) V CC = +3.3V ±10% or +2.5V ±5%; RL = 100Ω across each pair; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units V OH Output HIGH Voltage Q0, /Q0; Q1, /Q1 V CC–0.020 V CC V V OUT Output Voltage Swing Q0, /Q0; Q1, /Q1; see Figure 1a. 325 400 500 mV V DIFF_OUT Differential Voltage Swing Q0, /Q0; Q1, /Q1; see Figure 1b. 650 800 1000 mV R OUT Output Source Impedance Q0, /Q0; Q1, /Q1 40 50 60 Ω Notes: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. CML OUTPUT DC ELECTRICAL CHARACTERISTICS(6) |
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