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SY87729LHYTR Datasheet(PDF) 9 Page - Micrel Semiconductor |
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SY87729LHYTR Datasheet(HTML) 9 Page - Micrel Semiconductor |
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9 / 17 page  Micrel, Inc. SY87729L July 2011 9 M9999-072111-G hbwhelp@micrel.com Whereas P sets the integer part of the multiplication factor from input to output frequency, the control circuit determines the fractional part. By mixing the output of the P and P-1 dividers correctly, the control circuit can fashion any output frequency from P-1 times the input to P times the input, as long as that ratio can be expressed as a ratio of integers. Figure 2. 11/3 Example Figure 2 shows an example generating an output frequency 3⅔ times the input frequency. Since the output frequency is between 3 and 4 times the input, P is set to 4. We need to select the P divider twice, and select the P-1 divider once. Multiplying by 4 two times out of three, and multiplying by 3 one time out of three, averages to a multiplication of 3⅔. The top waveform is the reference input. The bottom waveform is the multiplied output. The waveform in the middle shows those edges from the output that most closely matches a corresponding reference waveform edge. The control circuit must generate a repeating pattern to the mux of something like “101,” so that the P divider is selected twice, and the P-1 divider is selected once, every three reference edges. Fractional-N Phase-Frequency Detector This circuit, besides generating “pump up” and “pump down” signals, also generates delta phase signals for use by the lock detect circuit. This detector circuit also accepts a gating signal from the Fractional-N control block. When gated, the phase detector generates neither pump up nor pump down pulses. Fractional-N Charge Pump This circuit converts the “pump up” and “pump down” signals from the phase-frequency detector into current pulses. An external loop filter integrates these current pulses into a control voltage. Charge pump current is selectable. This modifies loop gain as follows: During acquisition of the reference, the charge pump current is fixed at 20µA. Once the acquisition sequencer has completed center frequency trimming, then it changes the current of this charge pump to 50µA. Fractional-N VCO This circuit converts the voltage integrated by the external loop filter into a digital clock stream. The frequency of this clock varies based on this control voltage. This VCO has a coarse and a fine input, with a combined range of 540MHz to 729MHz. The coarse input trims the VCO, as described below, so that its center frequency rests near the target frequency to generate. The fine adjustment forms part of the closed loop. VCO gain is nominally 200MHz per volt. Fractional-N P/P-1 Divider This is the main divider for the fractional-N loop. The logical value of the output of the control block (Figure 1) defines whether the divider divides by P (values shown in Table 1) or by P-1. The expression for the fractional division becomes: Fractional Division = P ± ()⎥⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ + ± ± P Q 1 P Q 1 P Q Where QP is the number or reference clock periods during which the divider must divide by P and QP–1 is the number of reference clock periods during which the divider must divide by P-1. or (408) 955-1690 |
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