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SY88149HLMGTR Datasheet(PDF) 7 Page - Micrel Semiconductor |
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SY88149HLMGTR Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 11 page Micrel, Inc. SY88149HL June 2010 7 M9999-061110-I hbwhelp@micrel.com or (408) 955-1690 Functional Block Diagram Detailed Description The SY88149HL is a high-sensitivity limiting post amplifier which operates on a +3.3V power supply over the industrial temperature range. Signals with data rates up to 1.25Gbps and as small as 4mVpp can be amplified. Figure 1 shows the allowed input voltage swing. Depending upon the LOS/SDSEL option, the SY88149HL can generate an SD or LOS output, and allow feedback to the JAM input for output stability. LOS/SDLVL sets the sensitivity of the input amplitude detection. To satisfy the stringent timing requirements of the GPON specifications, the signal detect circuit offers 5ns SD assert (LOS de-assert) time and the option to de-assert SD (assert LOS) using the /AUTORESET or manual RESET function. When /AUTORESET is enabled, SD de-asserts/LOS asserts automatically within 100ns after the last high-to-low transition of the input burst. When the /AUTORESET function is disabled, the SD De- assert/LOS Assert time can be reset by using the provided RESET pin. Input Buffer Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 4mVpp to be detected and amplified. The input buffer can allow input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 48dB differential voltage gain until the outputs reach 1500mVPP (typ). Applications requiring the SY88149HL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88149HL’s input pins. This ensures the best performance of the device. Output Buffer The SY88149HL’s LVPECL output buffer is designed to drive 50 Ω lines. The output buffer requires appropriate termination for proper operation. An external 50 Ω resistor to VCC–2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage. Loss of Signal/Signal Detect The SY88149HL generates a chatter-free Signal-Detect (SD) or LOS LVTTL output, as shown in Figure 4. A highly sensitive signal detect circuit is used to determine that the input amplitude is too small to be considered a valid input. LOS asserts high if the input amplitude falls below the threshold set by LOS/SDLVL and de-asserts low otherwise. SD asserts high if the input amplitude rises above the threshold set by LOS/SDLVL and de-asserts low otherwise. LOS/SD can be fed back to the JAM input to maintain output stability under the absence of an invalid signal condition. Typically, a 3 dB hysteresis is provided to prevent chattering. LOS/SD Level Set A programmable LOS/SD level set pin (LOS/SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and LOS/SDLVL sets the voltage at LOS/SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF, as shown in Figure 5. Set the LOS/SDLVL voltage closer to VREF or more sensitive LOS/SD detection or closer to VCC for higher amplitude inputs. |
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