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SY89295U Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY89295U Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 17 page Micrel, Inc. SY89295U March 2011 5 M9999-032511 hbwhelp@micrel.com or (408) 955-1690 Pin Description Pin Number Pin Name Pin Function 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[9:0] CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See “AC Electrical Characteristics” for delay values. In addition, see “Interface Applications” section which illustrates the proper interfacing techniques for different logic standards. D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB). See “Typical Operating Characteristics” for delay information. 3 D10 CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended delay range. In addition, it drives CASCADE, and /CASCADE. Further, D[10] contains a pull-down and defaults LOW when left floating. 4, 5 IN, /IN LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75ký pull-down and will default to a logic LOW if left floating. 6 VBB (1) Reference Voltage Output: When using a single-ended input signal source to IN or /IN, connect the unused input of the differential pair to this pin. This pin can also be used to re-bias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01µF capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA. Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL.. Logic Standard VCF Connects to: LVPECL VEF, (1) CMOS No Connect 7 VEF TTL 1.5V Source 8 VCF Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for D[9:0], and D[10]. 9, 24, 28 GND, Exposed Pad(2) Negative Supply: For MLF ® package, exposed pad must be connected to a ground plane that is the same potential as the ground pin. 10 LEN ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0] and D[10] latches are transparent. 11 SETMIN ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left floating. 12 SETMAX ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10]. SETMAX contains a pull-down and defaults LOW when left floating. 13, 18, 19, 22 VCC Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors. 14, 15 /Cascade, Cascade LVPECL Differential Output: The outputs are used when cascading two or more SY89295U to extend the delay range. 16 /EN LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is a differential LOW. /EN contains a pull-down and defaults LOW when left floating. 20, 21 /Q, Q LVPECL Differential Output: Q is a delayed version of IN. Always terminate the output with 50Ω to VCC – 2V. See “Output Interface Applications” section. 17 NC No Connect. Notes: 1. Single-ended operation is only functional at 3.3V. 2. MLF ® package only. |
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