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SY89847UMGTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY89847UMGTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 15 page SY89847U 1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 2007 M9999-060107-B hbwhelp@micrel.com or (408) 955-1690 General Description The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer (MUX). A unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops significantly below 100mV). The differential input includes Micrel’s unique, 3-pin internal termination architecture that can interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are LVDS compatible with very fast rise/fall times guaranteed to be less than 210ps. The SY89847U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89847U is part of Micrel’s high-speed, Precision Edge ® product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Functional Block Diagram Precision Edge ® Features • Selects between two sources, and provides 5 precision LVDS copies • Fail-Safe Input – Prevents outputs from oscillating when input is invalid • Guaranteed AC performance over temperature and supply voltage: – DC-to >1.5GHz throughput – <1000ps Propagation Delay (IN-to-Q) – <210ps Rise/Fall times • Ultra-low jitter design: – <1psRMS random jitter – <1psRMS cycle-to-cycle jitter – <10psPP total jitter (clock) – <0.7psRMS MUX crosstalk induced jitter • Unique, patented MUX input isolation design minimizes adjacent channel crosstalk • Unique, patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) • Wide input voltage range VCC to GND • 2.5V ±5% supply voltage • -40°C to +85°C industrial temperature range • Available in 32-pin (5mm x 5mm) QFN package Applications • Fail-safe clock protection • Ultra-low jitter LVDS clock distribution • Rack-based Telecom/Datacom Markets • LAN/WAN • Enterprise servers • ATE • Test and measurement |
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