Micrel, Inc.

SY89852U

October 2008

M9999-100208-D

hbwhelp@micrel.com or (408) 955-1690

3

Pin Description

Pin Number

Pin Name

Pin Function

1,2,

3,4

IN, /IN

Differential Input: This input pair is the signal to be buffered. These inputs accept

internally terminates to a VT pin through 50

Ω. Note that this input will default to

an indeterminate state if left open. Please refer to the “Input Interface

Applications” section for more details.

16,5

VT

Input Termination Center-Tap: Each side of the differential input pair terminates

to this pin. The VT pin provides a center-tap to a termination network for

maximum interface flexibility. See “Input Interface Applications” section for more

details.

8,13

VCC

Positive Power Supply. Bypass with 0.1

µF0.01µF low ESR capacitors as close

12,9

Q, /Q

Differential 100K LVPECL Output: This LVPECL output is the output of the

device. Terminate through 50

Ω to V

PECL output requires DC path to

ground. Thus, AC-coupled applications require pull-down resistors. See “Output

Interface Applications” section.

10,11,14,15

GND,

Exposed Pad

Ground. Ground pin and exposed pad must be connected to the same ground

plane.

6

SEL

This single-ended TTL/CMOS-compatible input selects the inputs to the

multiplexer. Note that this input is internally connected to a 25K

Ω pull-up resistor

and will default to logic HIGH state if left open.

7

NC

No connect.

Truth Table

IN0

IN1

SEL

(1)

Q

0

X

0

0

1

X

0

1

X

0

1

0

X

1

1

1

Note:

1. SEL is connected to a 25k

Ω pull-up resistor and will default to logic high if left open.

Functional Block Diagram