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SY89873L

Micrel, Inc.

M9999-082407

hbwhelp@micrel.com or (408) 955-1690

DESCRIPTION

■ Guaranteed AC performance

•< 15ps within-device skew

•< 190ps rise/fall time

■ Low jitter design

■ Unique input termination and V

and AC-coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)

■ Precision differential LVDS outputs

■ Matched delay: all outputs have matched delay,

independent of divider setting

■ TTL/CMOS inputs for select and reset/disable

■ Two LVDS output banks (matched delay)

• Bank A: Buffered copy of input clock (undivided)

• Bank B: Divided output (

two copies

■ 3.3V power supply

■ Available in 16-pin (3mm ×

×

×

×

FEATURES

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

PROGRAMMABLE CLOCK DIVIDER

FANOUT BUFFER W/ INTERNAL TERMINATION

SY89873L

APPLICATIONS

■ SONET/SDH line cards

■ Transponders

■ High-end, multiprocessor servers

Rev.: F

Amendment: /0

Issue Date:

February 2007

This 3.3V low-skew, low-jitter, precision LVDS output clock

divider accepts any high-speed differential clock input (AC- or

DC-coupled) CML, LVPECL, HSTL or LVDS and divides down

the frequency using a programmable divider ratio to create a

frequency-locked, lower speed version of the input clock. The

SY89873L includes two output banks. Bank A is an exact

copy of the input clock (pass through) with matched

propagation delay to Bank B, the divided output bank. Available

divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock

system this would provide availability of 311MHz, 155MHz,

77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination

design that allows access to the termination network through

a VT pin. This feature allows the device to easily interface to

reference is included for AC-coupled applications.

The SY89873L is part of Micrel’s high-speed Precision

consider the SY89872U. For applications that require an

LVPECL output, consider the SY89871U.

The /RESET input asynchronously resets the divider outputs

(Bank B). In the pass-through function (Bank A) the /RESET

synchronously enables or disables the outputs on the next

falling edge of IN (rising edge of /N). Refer to the Timing

Diagram.

All support documentation can be found on Micrel’s web

site at: www.micrel.com.

FUNCTIONAL BLOCK DIAGRAM

TYPICAL APPLICATION

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

IN

50Ω

50Ω

/IN

S0

S1

QB1

/QB1

QB0

/QB0

QA

/QA

/RESET

Divided

by

2, 4, 8

or 16

Decoder

Enable

FF

Enable

MUX

IN

/IN

QA

/QA

622MHz LVDS

Clock Out

622MHz LVPECL

Clock In

622MHz/155.5MHz

SONET Clock Generator

Bank B: 155.5MHz: For OC-3 line card

Set to divide-by-4

Bank A: 622MHz: For OC-12 line card

Set to pass-through

155.5MHz LVDS

Clock Out

OC-12 or

OC-3

Clock Gen

QB

/QB