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SY898530UTZTX Datasheet(PDF) 3 Page - Micrel Semiconductor |
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SY898530UTZTX Datasheet(HTML) 3 Page - Micrel Semiconductor |
3 / 12 page Micrel, Inc. SY898530U November 2011 3 M9999-111011-C hbwhelp@micrel.com or (408) 955-1690 Pin Description Pin Number Pin Name Pin Function 36, 37 CLK, /CLK Differential Clock Inputs. Accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL logic levels. CLK is internally connected to a pull-down resistor, /CLK is internally connected to a pull- up resistor. See “Pin Characteristics” for typical values. 33, 34 31, 32 28, 29 26, 27 22, 23 20, 21 17, 18 15, 16 9, 10 7, 8 4, 5 2, 3 46, 47 44, 45 41, 42 39, 40 Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 Q10, /Q10 Q11, /Q11 Q12, /Q12 Q13, /Q13 Q14, /Q14 Q15, /Q15 LVPECL Differential Output Pairs. Differential buffered copies of the input signal. The output swing is typically 740mV. See Interface Applications for termination information. 1, 11, 14, 24, 25, 35, 38, 48 VCCO Output Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCCO pins as possible. Supplies the output buffers. 12, 13 VCC Core Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. Supplies input and core circuitry. 6, 19, 30, 43 VEE Ground Pin Characteristics Symbol Description Min. Typ. Max. Units CIN Input Capacitance 4 pF RPULLUP Input Pull Up Resistor 50 KΩ RPULLDOWN Input Pull Down Resistor 30 KΩ Clock Input Function Table Inputs Outputs CLK /CLK Qx /Qx Input to Output Mode Polarity 0 1 Low High Differential to Differential Non-Inverting 1 0 High Low Differential to Differential Non-Inverting 0 Biased (1) Low High Single-Ended to Differential Non-Inverting 1 Biased (1) High Low Single-Ended to Differential Non-Inverting Biased (1) 0 High Low Single-Ended to Differential Inverting Biased (1) 1 Low High Single-Ended to Differential Inverting Note: 1. Refer to Interface Applications for Single-Ended Interfaces. |
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