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R5F563NECDLC Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F563NECDLC Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 108 page  R01DS0098EJ0090 Rev.0.90 Page 11 of 106 Dec 27, 2011 RX63N Group, RX631 Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram ETHERC : Ethernet controller EDMAC : DMA controller for Ethernet controller ICUb : Interrupt controller DTCa : Data transfer controller DMACA : DMA controller EXDMACa : EXDMA controller BSC : Bus controller WDTA : Watchdog timer IWDTa : Independent watchdog timer CRC : CRC (cyclic redundancy check) calculator SCIc, SCId : Serial communications interface RSPI : Serial peripheral interface CAN : CAN module MTU2a : Multi-function timer pulse unit 2 POE2a : Port output enable 2 TPUA : 16-bit timer pulse unit PPG : Programmable pulse generator TMR : 8-bit timer CMT : Compare match timer RTCa : Realtime clock RIIC : I 2C bus interface IEB : IEBus controller External bus BSC Clock generati on circuit RX CPU RAM ROM Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C 10-bit ADC × 8 channels 12-bit ADC × 21 channels MTU2a × 6ch (unit 0) 10-bit DAC × 2 channel RIIC × 4ch USB 2.0 function module CAN × 3ch RTCa POE2a TPUa × 6ch (unit 1) IEB CMT × 2 channels (unit 1) CMT × 2 channels (unit 0) TMR × 2 channels (unit 1) TMR × 2 channels (unit 0) PPG (unit 1) PPG (unit 0) RSPI (unit 1) RSPI (unit 0) DTCa DMACA × 4ch ICUb Temperature sensor TPUa × 6ch (unit 0) RSPI (unit 2) USB 2.0 host/function module Port D Port E Port F Port G Port H Port J EDMAC ETHERC EXDMACa SCIc × 12ch WDTA E2 Data Flash CRC IWDTa SCId × 1ch |
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