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R5F52106ADFM Datasheet(PDF) 8 Page - Renesas Technology Corp |
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R5F52106ADFM Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 146 page R01DS0041EJ0090 Rev.0.90 Page 8 of 144 Aug 10, 2011 RX210 Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram External bus BSC ICU: Interrupt control unit DTC: Data transfer controller DMACA: DMA controller BSC: Bus controller WDT: Watchdog timer IWDT: Independent watchdog timer ELC: Event link controller CRC: CRC (cyclic redundancy check) calculator SCI: Serial communications interface RSPI: Serial peripheral interface RIIC: I 2C bus interface MTU2: Multi-function timer pulse unit 2 POE2: Port output enable 2 TMR: 8-bit timer CMT: Compare match timer RTC: Realtime clock DOC: Data operation circuit CAC: Clock-frequency accuracy measuring circuit Clock generation circuit RX CPU RAM ROM Port 0 Port 1 Port 2 Port 3 Port 4 10-bit D/A converter × 2 channels Temperature sensor RIIC × 1 channel DOC SCIc × 6 channels WDT E2 data flash CRC ELC RTC MTU2 × 6 channels 12-bit A/D converter × 16 channels CMT x 2 channels (unit 1) CMT x 2 channels (unit 0) TMR x 2 channels (unit 1) TMR × 2 channels (unit 0) RSPI × 1 channel DTC DMACA × 4 channels ICU CAC SCId × 1 channel Port 5 Port A Port B Port C Port D Port E Port H Port J POE2 IWDT Comparator B × 2 channels Comparator A × 2 channels |
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