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R5F56307DDLA Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R5F56307DDLA Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 165 page R01DS0060EJ0100 Rev.1.00 Page 4 of 168 Sep 13, 2011 RX630 Group 1. Overview Timers 16-bit timer pulse unit (TPUa) (16 bits × 6 channels) × 2 units Maximum of 16 pulse-input/output possible Select from among seven or eight counter-input clock signals for each channel Supports the input capture/output compare function Output of PWM waveforms in up to 15 phases in PWM mode Support for buffered operation, phase-counting mode (two phase encoder input) and cascade-connected operation (32 bits × 2 channels) depending on the channel. PPG output trigger can be generated Capable of generating conversion start triggers for the A/D converters Signals from the input capture pins are input via a digital filter Clock frequency measuring method Multi-function timer pulse unit 2 (MTU2a) (16 bits × 6 channels) × 1 unit Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/ output lines and three pulse-input lines Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/ 4, PCLK/16, PCLK/64, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5, for which only four signals are available. Input capture function 21 output compare/input capture registers Complementary PWM output mode Reset synchronous PWM mode Phase-counting mode Generation of triggers for A/D converter conversion Digital filter Signals from the input capture pins are input via a digital filter PPG output trigger can be generated Clock frequency measuring function Frequency measurement function (MCK) The MTU or unit 0 TPU module can be used to monitor the main clock, sub-clock, HOCO clock, LOCO clock, and PLL clock for abnormal frequencies. Port output enable 2 (POE2a) Controls the high-impedance state of the MTU’s waveform output pins Programmable pulse generator (PPG) (4 bits × 4 groups) × 2 units Pulse output with the MTU or TPU output as a trigger Maximum of 32 pulse-output possible 8-bit timers (TMR) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Compare match timer (CMT) (16 bits × 2 channels) × 2 units Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/ 512) Realtime clock (RTCa) Clock sources: Main clock, sub-clock Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Watchdog timer (WDTA) 14 bits × 1 channel Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/ 512, PCLK/2048, PCLK/8192) Independent watchdog timer (IWDTA) 14 bits × 1 channel Counter-input clock: Dedicated on-chip oscillator for IWDT Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 Table 1.1 Outline of Specifications (3/5) Classification Module/Function Description |
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