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SAF-C505-2RM Datasheet(PDF) 14 Page - Siemens Semiconductor Group |
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SAF-C505-2RM Datasheet(HTML) 14 Page - Siemens Semiconductor Group |
14 / 85 page Semiconductor Group 14 1997-12-01 C505 / C505C C505A / C505CA CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns. Special Function Register PSW (Address D0H) Reset Value : 00H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank Select Control Bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 P D0H PSW D7H D6H D5H D4H D3H D2H D1H D0H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00H-07H 0 1 Bank 1 selected, data address 08H-0FH 1 0 Bank 2 selected, data address 10H-17H 1 1 Bank 3 selected, data address 18H-1FH |
Similar Part No. - SAF-C505-2RM |
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Similar Description - SAF-C505-2RM |
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