New Product

R2A20158NP

Page 6 of 8

R03DS0015EJ0100 Rev.1.00

2010.09.05

Data Timing Chart SCL and SDA (Model)

< Start condition to slave address bit >

SDA

SCL

D/A

output

< Sub address bit >

SDA

SCL

D/A

output

Start condition

12

3

W

A

12

3

4

56

7

8

A

SDA

SCL

D/A

output

12

3

4

56

7

8

A

< DAC data bit to stop condition >

Stop

condition

 Start condition

With SCL at High, SDA line goes from High to Low

 Stop condition

With SCL at High, SDA line goes from Low to High

( Under normal circumstance, SDA is changed when SCL is Low )

 Acknowledge bit

The receiving IC has to pull down SDA line whenever receive slave data.

( The transmitting IC releases the SDA line just then transmit 8-bit data. )

4

56

7