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SX1512BIULTRT Datasheet(PDF) 23 Page - Semtech Corporation

Part No. SX1512BIULTRT
Description  World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine
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Maker  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
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SX1512BIULTRT Datasheet(HTML) 23 Page - Semtech Corporation

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ADVANCED COMMUNICATIONS & SENSING
Rev 4 – 26
th April 2011
23
www.semtech.com
SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
Addr
Name
Default
Bits
Description
0x00
RegInputDisable
0x00
7:0
Disables the input buffer of each [input-configured] IO
0 : Input buffer is enabled (input actually being used)
1 : Input buffer is disabled (input actually not being used or LED connection)
0x01
RegLongSlew
0x00
7:0
Enables increased slew rate of the output buffer of each [output-configured] IO
0 : Increased slew rate is disabled
1 : Increased slew rate is enabled
0x02
RegLowDrive
0x00
7:0
Enables reduced drive of the output buffer of each [output-configured] IO
0 : Reduced drive is disabled
1 : Reduced drive is enabled, IOL specifications are divided by 2.
0x03
RegPullUp
0x00
7:0
Enables the pull-up for each IO
0 : Pull-up is disabled
1 : Pull-up is enabled
0x04
RegPullDown
0x00
7:0
Enables the pull-down for each IO
0 : Pull-down is disabled
1 : Pull-down is enabled
0x05
RegOpenDrain
0x00
7:0
Enables open drain operation for each [output-configured] IO
0 : Regular push-pull operation
1 : Open drain operation
0x06
RegPolarity
0x00
7:0
Enables polarity inversion for each IO
0 : Normal polarity : RegData[x] = IO[x]
1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs)
0x07
RegDir
0xFF
7:0
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
0x08
RegData
0xFF
7:0
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
0x09
RegInterruptMask
0xFF
7:0
Configures which [input-configured] IO will trigger an interrupt on NINT pin
0 : An event on this IO will trigger an interrupt
1 : An event on this IO will NOT trigger an interrupt
7:6
Edge sensitivity of RegData[7]
5:4
Edge sensitivity of RegData[6]
3:2
Edge sensitivity of RegData[5]
0x0A
RegSenseHigh
0x00
1:0
Edge sensitivity of RegData[4]
00 : None
01 : Rising
10 : Falling
11 : Both
7:6
Edge sensitivity of RegData[3]
5:4
Edge sensitivity of RegData[2]
3:2
Edge sensitivity of RegData[1]
0x0B
RegSenseLow
0x00
1:0
Edge sensitivity of RegData[0]
00 : None
01 : Rising
10 : Falling
11 : Both
0x0C
RegInterruptSource
0x00
7:0
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
0x0D
RegEventStatus
0x00
7:0
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
7:6
Level shifter mode for IO[3] (Bank A) and IO[7] (Bank B)
5:4
Level shifter mode for IO[2] (Bank A) and IO[6] (Bank B)
3:2
Level shifter mode for IO[1] (Bank A) and IO[5] (Bank B)
0x0E
RegLevelShifter
0x00
1:0
Level shifter mode for IO[0] (Bank A) and IO[4] (Bank B)
00 : OFF
01 : A->B
10 : B->A
11 : Reserved
7
Unused
6:5
Oscillator frequency (fOSC) source
00 : OFF. LED driver, keypad engine and debounce features are disabled.
01 : External clock input (OSCIN)
10 : Internal 2MHz oscillator
11 : Reserved
4
OSCIO pin function (Cf. §4.7)
0 : OSCIO is an input (OSCIN)
1 : OSCIO is an output (OSCOUT)
0x0F
RegClock
0x00
3:0
Frequency of the signal output on OSCOUT pin:
0x0 : 0Hz, permanent "0" logical level (GPO)
0xF : 0Hz, permanent "1" logical level (GPO)
Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1))


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