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SX1512BIULTRT Datasheet(PDF) 13 Page - Semtech Corporation

Part No. SX1512BIULTRT
Description  World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine
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Maker  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
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SX1512BIULTRT Datasheet(HTML) 13 Page - Semtech Corporation

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ADVANCED COMMUNICATIONS & SENSING
Rev 4 – 26
th April 2011
13
www.semtech.com
SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
4.3
Reset
4.3.1
Hardware (NRESET)
The SX1511B and SX1512B generate their own power on reset signal after a power supply is connected to the
VDDM pin. NRESET input pin can be used to reset the chip anytime, it must be connected to VDDM (or greater)
either directly (if not used), or via a resistor.
Undefined
t
RESET
Reset
Signal
VDDM
VPOR
t
PULSE
VDROPH
Undefined
t
RESET
Undefined
1
2
3
4
5
6
2
1
VDROPL
Figure 6 – Power-On / Brown-out Reset Conditions
1. Device behavior is undefined until VDDM rises above VPOR, at which point internal reset procedure is
started.
2.
After tRESET, the reset procedure is completed.
3.
In operation, the SX1511B and SX1512B may be reset (POR like or LED driver counters only depending
on RegMisc setting) at anytime by an external device driving NRESET low for tPULSE or longer Chip can
be accessed normally again after NRESET rising edge.
4.
During a brown-out event, if VDDM drops above VDROPH a reset will not occur.
5.
During a brown-out event, if VDDM drops between VDROPH and VDROPL a reset may occur.
6.
During a brown-out event, if VDDM drops below VDROPL a reset will occur next time VPOR is crossed.
Please note that a brown-out event is defined as a transient event on VDDM. If VDDM is attached to a battery,
then the gradual decay of the battery voltage will not be interpreted as a brown-out event.
Please also note that a sharp rise in VDDM (> 1V/us) may induce a circuit reset.
4.3.2
Software (RegReset)
Writing consecutively 0x12 and 0x34 to RegReset register will reset all registers to their default values.
4.4
SPI Interface
The SX1511B and SX1512B SPI interface operates only in slave mode. 4 lines are used to exchange data
between an external master host and the slave device:
NSS : Slave select input (active low)
SCK : Clock input
SI : Data input
SO : Data output
The SX1511B and SX1512B have a few user-accessible internal 8-bits registers to set the various parameters of
operation (Cf. §5 for detailed configuration registers description). The SPI interface has been designed for
program flexibility, in that any register can be written or read independently of each other.


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