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ICE2PCS04G Datasheet(PDF) 11 Page - Infineon Technologies AG |
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ICE2PCS04G Datasheet(HTML) 11 Page - Infineon Technologies AG |
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11 / 20 page  CCM-PFC ICE2PCS04/G Functional Description Version 2.0 11 22 March 2010 voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC). 3.7 PWM Logic The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse T OFFMIN, are designed to meet a maximum duty cycle D MAX of 95% at the GATE output. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 13. Figure 13 PWM Logic 3.8 Voltage Loop The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage V OUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from V OUT. The pin VSENSE is the input of OTA1 which has an accurate internal reference of 3V (±2%). Figure 14 shows the important blocks of this voltage loop. 3.8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Figure 14). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up. Figure 14 Voltage Loop 3.8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a “window detector” for the feedback voltage V VSENSE at pin 6 (VSENSE). Whenever V VSENSE exceeds the reference value (3V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of V OUT. 3.9 Output Gate Driver The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 15V. G1 R S L1 R S L2 Peak Current Limit Current Loop PWM on signal Toffmin 385ns Current Limit Latch PWM on Latch HIGH = turn GATE on Q Q VCOMP VSENSE C5 C4 R6 OTA1 3V V IN Av(I IN) Nonlinear Gain t ICE2PCS04/G Vout L1 C2 R3 R4 Gate Driver Current Loop + PWM Generation D1 From Full-wave Retifier GATE R7 |
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