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MCM36F8 Datasheet(PDF) 8 Page - Motorola, Inc

Part No. MCM36F8
Description  1MB and 2MB Synchronous Fast Static RAM Module
Download  11 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCM36F8 Datasheet(HTML) 8 Page - Motorola, Inc

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MCM36F8
•MCM36F9
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.25 V
. . . . . . . . . . . . . .
Input Pulse Levels
0 to 2.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
1 V/ns (20 to 80%)
. . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 1 Unless Otherwise Noted
. . . . . . . . . . . . . .
DATA RAM READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
P
Sb l
MCM36F8 – 10
MCM36F9 – 10
Ui
N
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tKHKH
15
ns
Clock Access Time
tKHQV
10
ns
Output Enable to Output Valid
tGLQV
3.5
ns
Clock High to Output Active
tKHQX1
0
ns
5
Clock High to Output Change
tKHQX2
2
ns
5
Output Enable to Output Active
tGLQX
0
ns
5
Output Disable to Q High–Z
tGHQZ
3.5
ns
5, 6
Clock High to Q High–Z
tKHQZ
2
3.5
ns
5, 6
Clock High Pulse Width
tKHKL
4.5
ns
Clock Low Pulse Width
tKLKH
4.5
ns
Setup Times:
Address
ADSP
Data In
Write
Chip Enable
tAVKH
tADKH
tDVKH
tWVKH
tEVKH
2
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADX
tKHDX
tKHWX
tKHEX
0.5
ns
NOTES:
1. Write is defined as either any BWx and SW low or WE is low.
2. Chip Enable is defined as E0 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K0 or G0.
4. G0 is a don’t care after write cycle begins. To prevent bus contention, G0 should be negated prior to start of write cycle.
5. This parameter is sampled and not 100% tested.
6. Measured at
± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
50
VL = 1.25 V
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad-
dress setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.
Figure 1. AC Test Load


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