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MCM36F8 Datasheet(PDF) 6 Page - Motorola, Inc |
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MCM36F8 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 11 page ![]() MCM36F8 •MCM36F9 6 MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 through 4) Next Cycle Address Used Ex ADSP Gx DQx WRITE2, 4 Deselect None 1 0 X High–Z X Begin Read External 0 0 0 DQ Read Read Current X 1 1 High–Z Read Read Current X 1 0 DQ Read Begin Write External 0 0 X High–Z Write Write Current X 1 X High–Z Write NOTES: 1. X = don’t care, 1 = logic high, 0 = logic low. 2. Write is defined as either any BWx or WE low. 3. Gx is an asynchronous signal and is not sampled by the clock K. Gx drives the bus immediately (tGLQX) following Gx going low. 4. On write cycles that follow read cycles, Gx must be negated prior to the start of the write cycle to ensure proper write data setup times. Gx must also remain negated at the completion of the write cycle to ensure proper write data hold times. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VDD – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout – 0.5 to VDD + 0.5 V Output Current (per I/O) Iout ± 20 mA Temperature Under Bias Tbias – 10 to + 85 °C Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. |
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