Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

P1AFS600 Datasheet(PDF) 85 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 85 Page - Microsemi Corporation

Back Button P1AFS600 Datasheet HTML 81Page - Microsemi Corporation P1AFS600 Datasheet HTML 82Page - Microsemi Corporation P1AFS600 Datasheet HTML 83Page - Microsemi Corporation P1AFS600 Datasheet HTML 84Page - Microsemi Corporation P1AFS600 Datasheet HTML 85Page - Microsemi Corporation P1AFS600 Datasheet HTML 86Page - Microsemi Corporation P1AFS600 Datasheet HTML 87Page - Microsemi Corporation P1AFS600 Datasheet HTML 88Page - Microsemi Corporation P1AFS600 Datasheet HTML 89Page - Microsemi Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 85 / 334 page
background image
Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 - 69
Timing Characteristics
Table 2-31 • RAM4K9
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tAS
Address setup time
0.25 0.28 0.33
ns
tAH
Address hold time
0.00 0.00 0.00
ns
tENS
REN, WEN setup time
0.14 0.16 0.19
ns
tENH
REN, WEN hold time
0.10 0.11
0.13
ns
tBKS
BLK setup time
0.23 0.27 0.31
ns
tBKH
BL hold time
0.02 0.02 0.02
ns
tDS
Input data (DIN) setup time
0.18 0.21 0.25
ns
tDH
Input data (DIN) hold time
0.00 0.00 0.00
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
1.79 2.03 2.39
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
2.36 2.68 3.15
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
0.89 1.02 1.20
ns
tC2CWWH1
Address collision clk-to-clk delay for reliable write after write on same
address—Applicable to Rising Edge
0.30 0.26 0.23
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on
same address—Applicable to Opening Edge
0.45 0.38 0.34
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on
same address— Applicable to Opening Edge
0.49 0.42 0.37
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
0.92 1.05 1.23
ns
RESET Low to Data Out Low on DOUT (pipelined)
0.92 1.05 1.23
ns
tREMRSTB
RESET removal
0.29 0.33 0.38
ns
tRECRSTB
RESET recovery
1.50 1.71 2.01
ns
tMPWRSTB
RESET minimum pulse width
0.21 0.24 0.29
ns
tCYC
Clock cycle time
3.23 3.68 4.32
ns
FMAX
Maximum frequency
310
272
231
MHz
Notes:
1. For more information, refer to the application note
Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn