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P1AFS600 Datasheet(PDF) 71 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 71 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 - 55
tSUPGLOSSPRO
Page Loss Protect Setup Time for the Control Logic
1.69
1.93
2.27
ns
tHDPGLOSSPRO
Page Loss Protect Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUPGSTAT
Page Status Setup Time for the Control Logic
2.49
2.83
3.33
ns
tHDPGSTAT
Page Status Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUOVERWRPG
Over Write Page Setup Time for the Control Logic
1.88
2.14
2.52
ns
tHDOVERWRPG
Over Write Page Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSULOCKREQUEST
Lock Request Setup Time for the Control Logic
0.87
0.99
1.16
ns
tHDLOCKREQUEST
Lock Request Hold Time for the Control Logic
0.00
0.00
0.00
ns
tRECARNVM
Reset Recovery Time
0.94
1.07
1.25
ns
tREMARNVM
Reset Removal Time
0.00
0.00
0.00
ns
tMPWARNVM
Asynchronous Reset Minimum Pulse Width for the
Control Logic
10.00
12.50
12.50
ns
tMPWCLKNVM
Clock Minimum Pulse Width for the Control Logic
4.00
5.00
5.00
ns
tFMAXCLKNVM
Maximum Frequency for Clock for the Control Logic – for
AFS1500/AFS600
80.00
80.00
80.00
MHz
Maximum Frequency for Clock for the Control Logic – for
AFS250/AFS090
100.00
80.00
80.00
MHz
Table 2-25 • Flash Memory Block Timing (continued)
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units


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