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P1AFS600 Datasheet(PDF) 47 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 47 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 - 31
No-Glitch MUX (NGMUX)
Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence
between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses.
The NGMUX is used to switch the source of a global between three different clock sources. Allowable
inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in Figure 2-24.
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or
GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring
the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global
network (GL). See Table 2-13.
Figure 2-24 • NGMUX
Table 2-13 • NGMUX Configuration and Selection Table
GLMUXCFG[1:0]
GLMUXSEL[1:0]
Selected Input
Signal
MUX Type
00
X
0
GLA
2-to-1 GLMUX
X1
GLC
01
X
0
GLA
2-to-1 GLMUX
X
1
GLINT
Crystal Oscillator
RC Oscillator
W I/O Ring
CCC/PLL
Clock I/Os
From FPGA Core
PLL/
CCC
GLINT
GLA
GLC
NGMUX
GLMUXCFG[1:0]
PWR UP
GLMUXSEL[1:0]
GL
To Clock Rib Driver


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