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P1AFS600 Datasheet(PDF) 46 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 46 Page - Microsemi Corporation

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Device Architecture
2- 30
R e visio n 2
CCC and PLL Characteristics
Timing Characteristics
Table 2-12 • Fusion CCC/PLL Specification
Parameter
Min.
Typ.
Max.
Unit
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks1, 2
1603
ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
1.00%
1.00%
24 MHz to 100 MHz
1.50%
1.50%
100 MHz to 250 MHz
2.25%
2.25%
250 MHz to 350 MHz
3.50%
3.50%
Acquisition Time
LockControl = 0
300
µs
LockControl = 1
6.0
ms
Tracking Jitter4
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
0.6
5.56
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.025
5.56
ns
Delay Range in Block: Fixed Delay 1, 2
2.2
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-9 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.


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