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P1AFS600 Datasheet(PDF) 40 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 40 Page - Microsemi Corporation

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Device Architecture
2- 24
R e visio n 2
Notes:
1. Visit the Microsemi SoC Products Group website for application notes concerning dynamic PLL reconfiguration. Refer to
the "PLL Macro" section on page 2-29 for signal descriptions.
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
3. Refer to the
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for more information.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
Table 2-11 • Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS331
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKBUF_LVDS2
CLKBUF_LVPECL
Notes:
1. This is the default macro. For more details, refer to the
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library
Guide.
2. The B-LVDS and M-LVDS standards are supported with CLKBUF_LVDS.
PADN
PADP
Y
PAD
Y
Input LVDS/LVPECL Macro
INBUF2 Macro
GLA
or
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
Clock Source
Clock Conditioning
Output
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
CLKA
EXTFB
POWERDOWN
OADIVRST
GLA
LOCK
GLB
YB
GLC
YC


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