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P1AFS600 Datasheet(PDF) 28 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 28 Page - Microsemi Corporation

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Device Architecture
2- 12
R e visio n 2
Global Resources (VersaNets)
Fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry.
Each chip has six CCCs. The west CCC also contains a PLL core. In the two larger devices (AFS600 and
AFS1500), the west and the east CCCs each contain a PLL. The PLLs include delay lines, a phase
shifter (0°, 90°, 180°, 270°), and clock multipliers/dividers. Each CCC has all the circuitry needed for the
selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each
have access to three VersaNet global lines on each side of the chip (six lines total). The CCCs at the four
corners each have access to three quadrant global lines on each quadrant of the chip.
Advantages of the VersaNet Approach
One of the architectural benefits of Fusion is the set of powerful and low-delay VersaNet global networks.
Fusion offers six chip (main) global networks that are distributed from the center of the FPGA array
(Figure 2-11). In addition, Fusion devices have three regional globals (quadrant globals) in each of the
four chip quadrants. Each core VersaTile has access to nine global network resources: three quadrant
and six chip (main) global networks. There are a total of 18 global networks on the device. Each of these
networks contains spines and ribs that reach all VersaTiles in all quadrants (Figure 2-12 on page 2-13).
This flexible VersaNet global network architecture allows users to map up to 180 different
internal/external clocks in a Fusion device. Details on the VersaNet networks are given in Table 2-4 on
page 2-13. The flexibility of the Fusion VersaNet global network allows the designer to address several
design requirements. User applications that are clock-resource-intensive can easily route external or
gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce
delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global
network.
Figure 2-11 • Overview of Fusion VersaNet Global Network
Main (chip)
Global Network
Top Spine
Bottom Spine
Pad Ring
Chip (main)
Global Pads
Global
Pads
High-Performance
VersaNet Global Network
Global Spine
Global Ribs
Spine-Selection
Tree MUX
Quadrant Global Pads


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