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P1AFS600 Datasheet(PDF) 24 Page - Microsemi Corporation |
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P1AFS600 Datasheet(HTML) 24 Page - Microsemi Corporation |
24 / 334 page Device Architecture 2- 8 R e v ision 2 Array Coordinates During many place-and-route operations in the Microsemi Designer software tool, it is possible to set constraints that require array coordinates. Table 2-3 is provided as a reference. The array coordinates are measured from the lower left (0, 0). They can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os. Table 2-3 provides array coordinates of core cells and memory blocks. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and edge core cells. In addition, the I/O coordinate system changes depending on the die/package combination. It is not listed in Table 2-3. The Designer ChipPlanner tool provides array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment. Figure 2-7 illustrates the array coordinates of an AFS600 device. For more information on how to use array coordinates for region/placement constraints, see the Designer User's Guide or online help (available in the software) for Fusion software tools. Table 2-3 • Array Coordinates Device VersaTiles Memory Rows All Min. Max. Bottom Top Min. Max. x y x y (x, y) (x, y) (x, y) (x, y) AFS090 3 2 98 25 None (3, 26) (0, 0) (101, 29) AFS250 3 2 130 49 None (3, 50) (0, 0) (133, 53) AFS600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) AFS1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 129) Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. Figure 2-7 • Array Coordinates for AFS600 (0, 79) (197, 1) Top Row (5, 1) to (168, 1) Bottom Row (7, 0) to (165, 0) Top Row (169, 1) to (192, 1) Memory Blocks Memory Blocks Memory Blocks UJTAG FlashROM Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) I/O Tile (3, 77) (3, 76) Memory Blocks (3, 3) (3, 2) VersaTile (Core) (3, 75) VersaTile (Core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) VersaTile(Core) (194, 75) VersaTile (Core) (197, 79) (194, 77) (194, 76) I/O Tile to Analog Block |
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