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P1AFS600 Datasheet(PDF) 23 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Maker  MICROSEMI [Microsemi Corporation]
Homepage  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 23 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 -7
Sequential Timing Characteristics
Table 2-2 • Register Delays
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
0.55
0.63
0.74
ns
tSUD
Data Setup Time for the Core Register
0.43
0.49
0.57
ns
tHD
Data Hold Time for the Core Register
0.00
0.00
0.00
ns
tSUE
Enable Setup Time for the Core Register
0.45
0.52
0.61
ns
tHE
Enable Hold Time for the Core Register
0.00
0.00
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.40
0.45
0.53
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.40
0.45
0.53
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
0.00
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.22
0.25
0.30
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
0.00
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.22
0.25
0.30
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.22
0.25
0.30
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.22
0.25
0.30
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.32
0.37
0.43
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.36
0.41
0.48
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.


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