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P1AFS600 Datasheet(PDF) 21 Page - Microsemi Corporation

Part No. P1AFS600
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600 Datasheet(HTML) 21 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 -5
Timing Characteristics
Sample VersaTile Specifications—Sequential Module
The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library (Figure 2-5). For more details, refer to the IGLOO, ProASIC3,
SmartFusion and Fusion Macro Library Guide
.
Table 2-1 • Combinatorial Cell Propagation Delays
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
–2
–1
Std.
Units
INV
Y = !A
tPD
0.40
0.46
0.54
ns
AND2
Y = A · B
tPD
0.47
0.54
0.63
ns
NAND2
Y = !(A · B)
tPD
0.47
0.54
0.63
ns
OR2
Y = A + B
tPD
0.49
0.55
0.65
ns
NOR2
Y = !(A + B)
tPD
0.49
0.55
0.65
ns
XOR2
Y = A
Bt
PD
0.74
0.84
0.99
ns
MAJ3
Y = MAJ(A, B, C)
tPD
0.70
0.79
0.93
ns
XOR3
Y = A
B Ct
PD
0.87
1.00
1.17
ns
MUX2
Y = A !S + B S
tPD
0.51
0.58
0.68
ns
AND3
Y = A · B · C
tPD
0.56
0.64
0.75
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.


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