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AD5114 Datasheet(PDF) 18 Page - Analog Devices

Part No. AD5114
Description  Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5114 Datasheet(HTML) 18 Page - Analog Devices

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AD5111/AD5113/AD5115
Data Sheet
Rev. 0 | Page 18 of 24
THEORY OF OPERATION
The AD5111/AD5113/AD5115 digital programmable resistors
are designed to operate as true variable resistors for analog
signals within the terminal voltage range of GND < VTERM <
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register that allows unlimited changes of resistance settings.
The RDAC register can be programmed with any position
setting using the up/down interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of EEPROM data takes
approximately 30 ms; during this time, the device is locked and
does not accept any new operation, thus preventing any changes
from taking place.
The AD5111/AD5113/AD5115 are designed to allow high
speed digital control with clock rates up to 50 MHz.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
0x40 (AD5111), the wiper is connected to midscale of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
Once a desirable wiper position is found, this value can be
saved into the EEPROM. Thereafter, the wiper position is
always set at that position for any future on-off-on power
supply sequence or recall operation.
BASIC OPERATION
When CS is pulled low, changing the resistance settings is
achieved by clocking the CLK pin. It is negative edge triggered,
and the direction of stepping into the RDAC register is
determined by the state of the U/D input. When a specific state
of the U/D remains, the device continues to change in the same
direction under consecutive clocks until it comes to the end of
the resistance setting. When the wiper reaches the maximum or
minimum setting, additional CLK pulses do not change the
wiper setting. Figure 2 shows a typical increment/decrement
operation.
The U/D pin value can be changed only when the CLK pin
is low.
LOW WIPER RESISTANCE FEATURE
The AD5111/AD5113/AD5115 include a new feature to reduce
the resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 Ω to 45 Ω. At top scale, the
resistance between Terminal A and Terminal W is decreased by
1 LSB and the total resistance is reduced to 70 Ω. The new extra
steps are loaded automatically in the RDAC register after zero-
scale or full-scale position has been reached.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
SHUTDOWN MODE
This feature places Terminal A in open circuit, disconnected
from the internal resistor, and connects Terminal W and
Terminal B. A finite wiper resistance of 45 Ω is present between
these two terminals. The command is sent by a low-to-high
transition on the U/D pin, when CLK is high and CS is enabled.
The command is executed on the CLK negative edge, as shown
in Figure 4.
The AD5111/AD5113/AD5115 return the wiper to prior
shutdown position if any other operation is performed.
EEPROM WRITE OPERATION
The AD5111/AD5113/AD5115 contain an EEPROM that
allows the wiper position storage. Once a desirable wiper
position is found, this value can be saved into the EEPROM.
Thereafter, the wiper position is always set at that position for
any future power-up sequence or a memory recall operation.
During the storage cycle, the device is locked and does not accept
any new operation, thus preventing any changes from taking
place.
The write cycle is started by applying a pulse in the U/D pin
when CS is enabled and CLK remains high, as shown in
Figure 3. The write cycle takes approximately 20 ms.


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