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## AD5110 Datasheet(PDF) 15 Page - Analog Devices

 Part No. AD5110 Description Single-Channel, 64-Position, Push Button, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Download 16 Pages Scroll/Zoom 100% Maker AD [Analog Devices] Homepage http://www.analog.com Logo

## AD5110 Datasheet(HTML) 15 Page - Analog Devices

 15 / 16 page Data SheetAD5116Rev. 0 | Page 15 of 16PROGRAMMING THE POTENTIOMETER DIVIDERVoltage Output OperationThe digital potentiometer easily generates a voltage divider atwiper-to-B and wiper-to-A that is proportional to the inputvoltage at A to B, as shown in Figure 43. Unlike the polarity ofVDD to GND, which must be positive, voltage across A-to-B, W-to-A, and W-to-B can be at either polarity.WABVINVOUTFigure 43. Potentiometer Mode ConfigurationIf ignoring the effect of the wiper resistance for simplicity,connecting Terminal A to 5 V and Terminal B to groundproduces an output voltage at the Wiper W to Terminal Branging from 0 V to 5 V. The general equation defining theoutput voltage at VW, with respect to ground for any validinput voltage applied to Terminal A and Terminal B, is:BABAWAABWBWVRDRVRDRDV)()()((6)where:RWB(D)can be obtained from Equation 1 or Equation 2.RAW(D)can be obtained from Equation 3 to Equation 5 .Operation of the digital potentiometer in the divider moderesults in a more accurate operation over temperature. Unlikethe rheostat mode, the output voltage is dependent mainlyon the ratio of the internal resistors, RWA and RWB, and not theabsolute values. Therefore, the temperature drift reduces to5 ppm/°C.TERMINAL VOLTAGE OPERATING RANGEThe AD5116 is designed with internal ESD diodes forprotection. These diodes also set the voltage boundary ofthe terminal operating voltages. Positive signals present onTerminal A, Terminal B, or Terminal W that exceed VDD areclamped by the forward-biased diode. There is no polarityconstraint between VA, VW, and VB, but they cannot be higherthan VDD or lower than GND.POWER-UP SEQUENCEBecause of the ESD protection diodes that limit the voltagecompliance at Terminal A, Terminal B, and Terminal W (seeFigure 44), it is important to power on VDD before applyingany voltage to Terminal A, Terminal B, and Terminal W.Otherwise, the diodes are forward-biased such that VDD ispowered on unintentionally and can affect other parts of thecircuit. Similarly, VDD should be powered down last. The idealpower-on sequence is in the following order: GND, VDD, andVA/VB/VW. The order of powering VA, VB, and VW is notimportant as long as they are powered on after VDD. Thestates of the PU and PD pins can be logic low or floating,but they should not be logic high during power-on.GNDVDDAWBFigure 44. Maximum Terminal Voltages Set by VDD and VSSLAYOUT AND POWER SUPPLY BIASINGIt is always a good practice to use compact, minimum leadlength layout design. The leads to the input should be as directas possible with a minimum conductor length. Ground pathsshould have low resistance and low inductance. It is also goodpractice to bypass the power supplies with quality capacitors.Low equivalent series resistance (ESR) 1 μF to 10 μF tantalumor electrolytic capacitors should be applied at the supplies tominimize any transient disturbance and to filter low frequencyripple. Figure 45 illustrates the basic supply bypassing config-uration for the AD5116.AD5116C210µFC10.1µFVDDVDDAGNDGND+Figure 45. Power Supply Bypassing