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AD5112 Datasheet(PDF) 19 Page - Analog Devices |
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AD5112 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 28 page 
Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 19 of 28 THEORY OF OPERATION The AD5110/AD5112/AD5114 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of GND < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface. Once a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of EEPROM data takes approximately 18 ms; during this time, the device is locked and does not acknowledge any new command, thus preventing any changes from taking place. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x3F (128-taps), the wiper is connected to full scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the I2C interface (see Table 10). The contents of the RDAC register can be stored to the EEPROM using Command 1 (Table 10). Thereafter, the RDAC register is always set at that position for any future on-off-on power supply sequence. It is possible to read back the data saved into the EEPROM with Command 6 in Table 10. In addition, the resistor tolerance error is saved within the EEPROM; this can be read back and used to calculate the end- to-end tolerance, providing an accuracy of 0.1%. Low Wiper Resistance Feature The AD5110/AD5112/AD5114 include extra steps to achieve a minimum resistance between Terminal W and Terminal A or Terminal B. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 70 Ω. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. I2C SERIAL DATA INTERFACE The AD5110/AD5112/AD5114 have 2-wire I2C-compatible serial interfaces. These devices can be connected to an I2C bus as a slave device under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD5110/AD5112/AD5114 support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. 3. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 4. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low before the 10th clock pulse, and high during the 10th clock pulse to establish a stop condition. I2C Address The AD5110/AD5112/AD5114 each have two different slave address options available. See Table 9 for a list of slave addresses. Table 9. Device Address Selection Model 7-Bit I2C Device Address AD511X1 BCPZ Y2 0101111 AD511X1 BCPZ Y2-1 0101100 1 Model. 2 Resistance. |
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